Reusable Intellectual Property Research Articles

Using Pattern of On-Off Routers and Links and Router Delays to Protect Network-on-Chip Intellectual Property

Intellectual Property (IP) reuse is a well known practice in chip design processes. Nowadays, network-on-chips (NoCs) are increasingly used as IP and sold by various vendors to be integrated in a multiprocessor system-on-chip (MPSoC). However, IP reuse exposes the design to IP theft, and an attacker can launch IP stealing attacks against NoC IPs. With the growing adoption of MPSoC, such attacks can result in huge financial losses. In this article, we propose four NoC IP protection techniques using fingerprint embedding: ON-OFF router-based fingerprinting (ORF), ON-OFF link-based fingerprinting (OLF), Router delay-based fingerprinting (RTDF), and Row delay-based fingerprinting (RWDF). ORF and OLF techniques use patterns of ON-OFF routers and links, respectively, while RTDF and RWDF techniques use router delays to embed fingerprints. We show that all of our proposed techniques require much less hardware overhead compared to an existing NoC IP security solution (square spiral routing) and also provide better security from removal and masking attacks. In particular, our proposed techniques require between 40.75% and 48.43% less router area compared to the existing solution. We also show that our solutions do not affect the normal packet latency and hence do not degrade the NoC performance.

Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems

In the prior articles of reusable intellectual property (IP) core, different facets of their threat models and defence mechanisms against IP Trojan and IP piracy have been presented. This article provides novel comparative perspective between the two security techniques viz. palmprint biometric based approach and encrypted hash-based digital signature approach for IP cores, integrated in Consumer Electronics systems. These reusable IP cores such as finite impulse response filter used in audio devices, HD TVs, etc., discrete cosine transform core used in audio/image/video/compression, fast Fourier transform used in digital video broadcasting and JPEG-CODEC used in image/video compression of camera systems can be secured using the two security methodologies discussed in this article. These both approaches enable detective control against important security threats such as IP piracy, fraudulent claim of IP ownership, overproduction, and IP counterfeiting. The article therefore contributes the following: 1) security comparison of security techniques on digital signal processing IP cores in terms of probability of coincidence and tamper tolerance, 2) comparison between two security techniques in terms of its properties, 3) end to end demonstration of the palmprint biometric security approach, and 4) design flow of the encrypted hash-based digital signature approach.

Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric

This paper presents a novel methodology to design a secured custom reusable intellectual property (IP) core for the convolutional layer of convolutional neural network (CNN). Since the reusable IP cores used in system-on-chips (SoCs) of consumer electronics (CE) systems are susceptible to the hardware threat of IP counterfeiting. Therefore, this paper also presents the security of the proposed convolutional layer reusable IP core against the threat of IP counterfeiting using facial biometrics. This enables the integration of secured reusable IP cores in the SoCs of CE systems, thereby ensuring the safety of end consumers. In the proposed approach, the convolutional layer IP core is designed through high-level synthesis (HLS) process and secured by embedding secret biometric security information into the design during register allocation phase of the HLS process. The qualitative and quantitative analysis of the proposed approach exhibits significantly lower probability of coincidence (Pc) (up to 47% less) and higher tamper tolerance (1.93E+25) than recent approaches. Further, it offers robust security with zero design overhead.

Design and verification of SPI bus IP core

With the development of chip design technology, the complexity of the chip is getting bigger and bigger, and various IP (Intellectual Property) is integrated to form SoC (System on Chip). In order to improve the efficiency of designing SoC, IP reuse technology is often used, so the development of IP has a wide range of significance and use value. The SPI bus is a bus protocol often used in chip communication and has many application scenarios. Therefore, this research mainly develops the SPI bus IP. During the development process, the SPI bus design is carried out, then based on the UVM verification methodology the designed IP has been functionally verified, and finally, a fully functional SPI bus design is obtained.

HLS Based IP Protection of Reusable Cores Using Biometric Fingerprint

Reusable Intellectual property (IP) cores are increasingly being integrated in system-on-chips (SoCs) to reduce the SoC design complexity and satisfy the time to market constraint. However, globalization of design supply chain renders the IP cores such as digital signal processer (DSP) hardware accelerators vulnerable to piracy threat. Additionally, integrated circuits (ICs)/ IPs can be fraudulently claimed by a dishonest user. This letter presents a novel biometric fingerprint based hardware security approach using high level synthesis (HLS) framework to safeguard an IC/ IP against false ownership claim and piracy. The proposed approach embeds the IP vendor's biometric fingerprint into a hardware accelerator in the form of secret security constraints. Results show that the proposed approach outperforms a recent approach in terms of enhanced security.

Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation

To preserve the SystemC semantics under parallel discrete event simulation, a compiler based approach statically analyzes race conditions in the design model. However, there are severe restrictions: the source code for the input design must be available in one file, which does not scale. This disables the use of intellectual property (IP) and hierarchical file structures. This paper scales the static analysis design flow to support separate files and IP reuse by introducing partial segment graph and partial port mapping abstractions and prevent IP security leakage. Experiments demonstrate the effective design flow and sustained speedup with parallel IPs.

Resource Efficient Metering Scheme for Protecting SoC FPGA Device and IPs in IoT Applications

Due to the fact that most of the functions in SoC are handled by the intellectual property (IP) blocks, the CPU plays a minimum role in scheduling the functionality of the IP blocks wherever IP reuse is vital in order to increase the performance and to reduce the resource utilization, cost, and power. This paper aims to propose a hardware-based metering scheme to execute the preferred typing mistake IP (IPs) in a specific SoC FPGA and protect both device and IPs from cloning, misuse, and attacks. The metering service emphasizes a license using a hybrid physical unclonable function (PUF) and finite-state machine (FSM), which hold considerable advantages. The enrolment and activation protocol has been used to authenticate, control, and monitor the Internet of Things (IoT) IPs in an SoC FPGA device. The experimental results show that the resource utilization and power consumption are 8% and 1%, respectively, for activating and executing the IoT IP service with an average delay of 6.6 s. The proposed scheme is implemented in 28-nm FPGAs to secure the chip and IPs and is also compared with recent schemes.

Accelerator Design for Ethernet and HDMI IP Systems for IoT using Xilinx Vivado 18.X

Xilinx Vivado software is used for designing synthesis and implementation of accelerator. The objective of this paper is to understand the concept of intellectual property (IP), IP reuse, custom IP and IP subsystem and to design the subsystem using Xilinx Vivado is used. This paper attempts to design accelerator to make communication possible between High Definition Multimedia Interface (HDMI) and Ethernet for Internet of Things (IoT) using Xilinx Vivado 18.X [4]. The term is increasingly being also defined as objects that “talk” to each other rather in the manner of Internet of Learning Things (IoLT) based IoT to define objects with that of “realistically talk” to each other, given the rising system external & internal environmental complexity and uncertainty factors facing the objects.

Embedding Digital Signature Using Encrypted-Hashing for Protection of DSP Cores in CE

Reusable intellectual property (IP) cores from signal processing and multimedia form an integral part of consumer electronics (CE) systems. However, owing to the value it represents, it needs protection against important threats, such as piracy and illegal claim of ownership. This paper presents a novel multi-level encoding and encrypted-hash-based digital signature for protection of complex reusable IP core used in CE systems. For the first time in the literature, a digital signature-based IP core protection is proposed for digital signal processing (DSP) kernels. The proposed methodology is capable of encoding a DSP kernel application, followed by creating a digest of the encoded application to finally form a digital signature using RSA, which is subsequently implanted into the same design during architectural synthesis. The proposed approach on DSP benchmarks is capable of achieving higher robustness in terms of lower probability of coincidence - indicating stronger proof of authorship. The proposed approach achieves stronger robustness (on average by ~24.8%) as well as requires lesser storage hardware (on average reduction of ~14%) compared to similar prior work.

Robust Logic locking for Securing Reusable DSP Cores

A System on Chip (SoC) used in Consumer Electronics (CE) systems integrates a number of reusable Intellectual Property (IP) cores from digital signal processing (DSP), multimedia etc. However, these DSP based IP cores are susceptible to various hardware threats such as piracy, Trojan insertion, overbuilding and reverse engineering. Thus, security of DSP cores is very crucial. An IP core can be secured against aforementioned hardware threats by employing logic locking based security mechanisms. This paper presents a novel robust logic locking using hybrid locking cells for securing DSP cores. The proposed logic locking is based on a novel advanced encryption standard (AES) based reconfigurable hybrid locking cell architecture that ensures strong security against key sensitization, removal and SAT attacks. The strength of the proposed approach has been assessed in terms of probability of obtaining correct key of a locked design in exhaustive trials. Results of proposed work on DSP cores yielded higher logic locking strength and lower design overhead compared to recent prior works.

Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis

Reusable intellectual property (IP) cores used in the consumer electronic devices, representing years of valuable investment, need protection against threats such as piracy and illegal claim of ownership. This paper introduces a novel 7-variable signature encoding driven triple-phase watermarking methodology during high level synthesis (HLS)/architectural synthesis for IP core protection of vendor rights. The proposed approach is extremely robust against external threats as it involves vendor signature comprising of 7-variable combination embedded through three independent phases of HLS. This paper is the first work in the HLS literature that presents a triple-phase watermarking process during HLS compared to single phase watermarking techniques so far. The proposed approach incurs zero delay overhead and minimal hardware overhead while embedding as well as yields average cost reductions of 7.38% and 6.25% compared to two similar approaches. Further, the proposed triple-phase watermark approach achieves a lower ${P} _{c}$ value by ~ ${3.2} {\times}\,10^{27}$ times in magnitude compared to similar approaches. Additionally, the proposed approach is 3.4 ${\times } {10}^{43}$ and 2.8 ${\times } {10}^{19}$ times more tamper tolerant than similar approaches.

Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters]

The surging design productivity of modern consumer electronics (CE) devices has only been possible due to the employment of reusable intellectual property (IP) cores in its hardware design. However, the IP core design process is vulnerable to threats in the design flow such as reverse-engineering attacks that aim to clone (and pirate) or insert malicious Trojan logic in the design netlist. Thus, the key is protecting the IP design netlist from unwanted access. This article proposes an IP core with a low-cost functional locking methodology that safeguards the design netlist from rogue elements in design flow intending attacks. The presented approach achieves cost reduction of functionally locked IP core design and enhanced security against reverse-engineering attacks.

Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis

Reusable Intellectual Property (IP) cores have become an obligatory mandate for combating conflicting objectives of maximizing design productivity and minimizing design cycle time. However, a reusable IP core needs protection against false (illegal) claim of ownership. In this paper, we propose a novel computational forensic engineering (CFE) based approach for resolving ownership problem of a reusable IP core generated during high level synthesis (HLS).Some of the major contributions of the proposed approach are as follows: (a) a novel methodology based on multiple design feature set (technology & control parameter independent) that is capable of resolving false claim of vendor ownership problem for an IP core generated during HLS (b) novel algorithms for extracting design features (from register transfer level (RTL) hardware description language (HDL)) of an IP core for determining the rightful owner (c) a novel signature free approach (with avg. runtime ∼2 s) that offers 0% hardware overhead and 0% degradation of IP functionality/quality compared to watermarking based IP ownership resolution techniques.

Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools

This paper presents a novel low cost scheduling driven watermarking methodology for modern computer aided design (CAD) high level synthesis tools. The proposed watermarking algorithm is embedded in the scheduling module of a CAD high level synthesis (HLS) tool. The presented watermarking methodology is capable of reusable intellectual property (IP) core protection of control data flow graphs (CDFG) from a vendor's perspective based on user provided resource constraint and loop unrolling factor as inputs. The proposed low cost robust watermarking embedded inside high level synthesis process protects an IP core against threats such as false claim of ownership and piracy. The proposed watermarking satisfies desirable properties such as covertness, robustness, low embedding cost and low complexity. Results of comparison indicated significant reduction in embedding cost through proposed technique than similar state of the art techniques.

Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis

Intellectual Property (IP) core used in computing system-on-chip provides a unique blend of yielding enhanced design productivity with reduced design cycle time. However, leveraging benefits of IP core require protection against threats from both seller’s and buyer’s perspective. This paper proposes a novel symmetrical IP core protection methodology that embeds a buyer fingerprint and seller watermark simultaneously during high level synthesis (HLS). The proposed work leverages major HLS steps to concurrently embed buyer fingerprint signature and seller watermark signature into a reusable IP core design. The proposed signature encoding for fingerprint and watermark is multi-variable in nature offering strong robustness, low embedding cost and low design overhead. Results on standard benchmarks indicated that the proposed symmetrical approach satisfies all the major protection features of a watermark and fingerprint such as strong robustness to both seller & buyer, low overhead, low runtime and low embedding cost. Further on comparison with baseline design (no protection), the proposed approach offers symmetrical protection (both buyer and seller) at less than 1% area overhead and less than 1.1% latency overhead. Additionally on comparison with a recent unsymmetrical approach, the proposed approach offers symmetrical protection (both buyer and seller) at 0% area overhead and less than 1.1% latency overhead.

Hardware Security of CE Devices [Hardware Matters]

In my previous columns, I have covered various topics, including the evolution of the intellectual property core industry, digital integrated circuit (IC) design flow, high-level perspectives on intellectual property (IP) cores, and the transient fault resiliency of IP cores. Though one of my previous columns focused on providing a generic cognizance about the protection of reusable IP cores, it did not delve deep into the threat models and defense mechanisms against hardware trojans and IP piracy. This column discusses hardware security of consumer electronics (CE) devices, focusing primarily on threat models and defense mechanisms against two major attacks: hardware trojans and IP piracy.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices

It is a well-known fact that design productivity is failing to keep pace with the big increase in the demands of applications and advanced silicon technology, especially in the domain of portable electronics. Moreover owing to the massive complexity of modern systems-on-chip (SoC), complete in-house development is impossible, and thus globalization of the design process has established itself as an inevitable solution for faster and efficient design. In this global design supply chain, the design of mobile computing devices relies heavily on reusable Intellectual Property (IP) cores as a practical solution. However, such IP cores are becoming increasingly vulnerable to malicious activities, attacks and threats. Any form of third party intervention in the design process can raise grave security concerns about the system. Security issues in IP’s can be in the form of IP piracy/IP counterfeit or embedded malicious logic or information leakage. The first form of security countermeasure requires anti-piracy methodologies that can nullify false claims of ownership or detect unauthorized pirated designs. The second form of threat, which is often called a ‘hardware Trojan’, is the deliberate insertion of illicit hardware into the IP design by a rogue designer or vendor, also requires detection/correction strategies as a security countermeasure.

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

The challenges in the current design process for consumer electronics products include greater complexity and stiff time-to-market pressure, which has led to the usage of reusable intellectual property (IP) cores (such as JPEG and MPEG) as a sustainable solution. This has led to the domain of IP protection for anti-piracy as an important subject of research for a system design. Watermarking is expected to provide the best protection of authorship when applied at higher levels, i.e., during high-level synthesis. It is also well acknowledged that watermark insertion is non-trivial, as it is very difficult to choose a strong signature that results in higher security and less area overhead among available design solutions. This paper presents a novel multi-variable signature encoding for embedding a dynamic watermark in an IP design during architectural synthesis that provides enhanced security against typical attacks. Owing to the involvement of multiple (four) variables in the proposed signature, it is difficult to realize the signature without complete encoding knowledge of the four variables. Second, our approach aims to optimize the embedding cost of the watermark by exploring a low-cost solution through particle swarm optimization-driven design space exploration based on area-delay constraints. Comparison with a recent technique indicated that our watermark incurs lower embedding cost, lower runtime, and less storage hardware.

FPGA-based many-core System-on-Chip design

Massively parallel architectures are proposed as a promising solution to speed up data-intensive applications and provide the required computational power. In particular, Single Instruction Multiple Data (SIMD) many-core architectures have been adopted for multimedia and signal processing applications with massive amounts of data parallelism where both performance and flexible programmability are important metrics. However, this class of processors has faced many challenges due to its increasing fabrication cost and design complexity. Moreover, the increasing gap between design productivity and chip complexity requires new design methods. Nowadays, the recent evolution of silicon integration technology, on the one hand, and the wide usage of reusable Intellectual Property (IP) cores and FPGAs (Field Programmable Gate Arrays), on the other hand, are attractive solutions to meet these challenges and reduce the time-to-market. The objective of this work is to study the performances of massively parallel SIMD on-chip architectures with current design methodologies based on recent integration technologies. Flexibility offered by these new design tools allows design space exploration to search for the most effective implementations. This work introduces an IP-based design methodology for easy building configurable and flexible massively parallel SIMD processing on FPGA platforms. The proposed approach allows implementing a generic parallel architecture based on IP assembly that can be tailored in order to better satisfy the requirements of highly-demanding applications. The experimental results show effectiveness of the design methodology as well as the performances of the implemented SoC.